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| LH5324C00 FEATURES * 1,572,864 x 16 bit organization * Access time: 120 ns (MAX.) * Supply current: - Operating: 80 mA (MAX.) - Standby: 100 A (MAX.) * TTL compatible I/O * Three-state output * Single +5 V Power supply * Static operation * When the address input at both A19 and A20 is high level, outputs become high impedance irrespective of CE or OE. * Package: 42-pin, 600-mil DIP * Others: - Non programmable - Not designed or rated as radiation hardened - CMOS process (P type silicon substrate) DESCRIPTION The LH5324C00 is a 24M-bit mask-programmable ROM organized as 1,572,864 x 16 bits. It is fabricated using silicon-gate CMOS process technology. 42-PIN DIP CMOS 24M (1.5M x 16) MROM PIN CONNECTIONS TOP VIEW A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE D0 D8 D1 D9 D2 D10 D3 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 A20 GND D15 D7 D14 D6 D13 D5 D12 D4 VCC 5324C00-1 Figure 1. Pin Connections 1 LH5324C00 CMOS 24M (1.5M x 16) MROM A20 32 A19 42 A18 1 A17 2 A16 33 A15 34 A14 35 MEMORY MATRIX (1,572,864 x 16) 30 D15 28 D14 ADDRESS BUFFER A10 39 A9 40 A8 41 A7 3 A6 4 A5 5 A4 A3 A2 6 7 8 DATA SELECTOR/OUTPUT BUFFER A13 36 A12 37 A11 38 ADDRESS DECODER 26 D13 24 D12 21 D11 19 17 15 29 D10 D9 D8 D7 27 D6 25 D5 23 D4 20 D3 18 D2 16 D1 14 D0 COLUMN SELECTOR A1 9 A0 10 CE 11 CE BUFFER TIMING GENERATOR SENSE AMPLIFIER OE 13 OE BUFFER 22 VCC 12 31 GND 5324C00-2 Figure 2. LH5324C00 Block Diagram PIN DESCRIPTION SIGNAL PIN NAME SIGNAL PIN NAME A0 - A20 D0 - D15 CE Address input Data output Chip enable input OE VCC GND Output enable input Power supply (+5 V) Ground 2 CMOS 24M (1.5M x 16) MROM LH5324C00 TRUTH TABLE CE OE A0 - A18 A19 A20 DATA OUTPUT D0 - D15 SUPPLY CURRENT H L L L L L X H L L L L X X X X X X X X L L H H X X L H L H High-Z High-Z Output Output Output High-Z Standby (ISB ) Operating (ICC) Operating (ICC) Operating (ICC) Operating (ICC) Operating (ICC) NOTES: 1. X = Don't care; High-Z = High-impedance 2. When the address inputs become HIGH to both A19 and A20, the data does not exist in this address area, the data outputs become "High Impedance". ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage Input voltage Output voltage Operating temperature Storage temperature VCC VIN VOUT TOPR TSTG -0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 0 to +70 -65 to +150 V V V C C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage VCC 4.5 5.0 5.5 V DC ELECTRICAL CHARACTERISTICS (VCC = 5 V 10%, TA = 0 to +70C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Input `High' voltage Input `Low' voltage Output `High' voltage Output `Low' voltage Input leakage current Output leakage current Operating current V IH VIL VOH VOL | ILI | | ILO | ICC1 ICC2 I OH = -400 A I OL = 2.0 mA V IN = 0 V to VCC V OUT = 0 V to VCC t RC = 120 ns t RC = 1 s CE = VIH CE = VCC - 0.2 V f = 1 MHz, t A = 25C 2.2 -0.3 2.4 VCC + 0.3 0.8 0.4 10 10 80 70 2 100 10 10 V V V V A A mA mA A pF pF 1 2 Standby current Input capacitance Output capacitance ISB1 ISB2 CIN COUT NOTES: 1. CE = VIH, OE = VIH 2. VIN = VIH or VIL, CE = VIL, output is open 3 LH5324C00 CMOS 24M (1.5M x 16) MROM AC ELECTRICAL CHARACTERISTICS (VCC = +5 V 10%, TA = 0 to +70C) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read cycle time Address access time Chip enable access time Output enable delay time Output hold time tRC tAA tACE tOE tOH tCHZ 120 0 120 120 60 50 50 60 ns ns ns ns ns ns ns ns Output floating time tOHZ tAHZ 1 NOTE: 1. Determined by the time for the output to be opened. (Irrespective of output voltage) AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude Input signal rise time Input signal fall time Input reference level Output reference level Output load condition 0.6 V to 2.4 V 10 ns 10 ns 1.5 V 1.5 V 1TTL + 100 pF NOTE: It is recommended that a decoupling capacitor be connected between VCC and GND-Pin. 4 CMOS 24M (1.5M x 16) MROM LH5324C00 tRC A0 - A20 tAA (NOTE) CE tACE (NOTE) OE tOE (NOTE) tOH HI-Z tOHZ tCHZ D0 - D15 HI-Z DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. HI-Z = High Impedance. 5324C00-3 Figure 3. Byte Mode A0 - A18 A19, A20 CE tCHZ OE tOHZ tAHZ HI-Z HI-Z D0 - D15 DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. HI-Z = High impedance. 5324C00-4 Figure 4. Word Mode 5 LH5324C00 CMOS 24M (1.5M x 16) MROM PACKAGE DIAGRAM 42DIP (DIP042-P-0600) 42 22 DETAIL 13.45 [0.530] 12.95 [0.510] 0 TO 15 1 54.10 [2.130] 53.50 [2.106] 4.55 [0.179] 3.95 [0.156] 5.40 [0.213] 4.80 [0.189] 3.55 [0.140] 2.95 [0.116] 2.54 [0.100] TYP. 0.90 [0.035] TYP. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT 15.24 [0.600] TYP. 21 0.30 [0.012] 0.20 [0.008] DIMENSIONS IN MM [INCHES] 42DIP ORDERING INFORMATION LH5324C00 Device Type D Package 42-pin, 600-mil DIP (DIP42-P-600) CMOS 24M (1.5M x 16) Mask-Programmable ROM Example: LH5324C00D (CMOS (24M 1.5M x 16) Mask-Programmable ROM, 42-pin, 600-mil DIP) 5324C00-5 6 |
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